1. Field of the Invention
The present invention generally relates to methods of making semiconductor devices, and more particularly to a method of using dielectric etch stop layers to reduce or eliminate emitter defects during bipolar transistor fabrication.
2. Description of the Related Art
A process for fabricating high performance bipolar transistors is described in Konaka et al., "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology," IEEE Trans. Electronic Devices, Vol. ED-33, pp. 526-531, Apr. 1986. The process includes a self-align technique using a single optical mask to provide the active regions of the transistor, including the emitter, emitter-base spacing, and the base contacts. In this process, however, unacceptable damage to the silicon surface, particularly in the emitter region, may occur during the etching away of device layers overlying the active area surface. Other self-align methods have similarly failed to avoid unacceptable damage to a semiconductor surface in an active area during fabrication steps. Preventing such damage is especially difficult during etching steps in which it is desirable to form very precise regions in the layers overlying the active area of the semiconductor substrate.
Transistor fabrication methods which do not adequately prevent emitter region damage, as described above, result in poorer and lower manufacturability of high performance bipolar transistors, less uniform device characteristics, and relatively low chip yields.
Accordingly, an object of the present invention is to avoid or minimize the above mentioned problems.